Tech Stack

Description

You will work on UVM testbench techniques, real number modeling, and AMS verification for integrated digital, analog, and photonic devices. You'll collaborate with architects and designers to define validation flows and drive DV methodologies, ensuring high-quality tapeouts.

Requirements

• Bachelor's degree in EE/CE or equivalent
• 8+ years of design verification and SystemVerilog experience
• 2+ years of Python experience
• Expertise in UVM library
• Experience with simulators like Xcelium, ModelSim, Questa, or VCS

Responsibilities

• Define and enhance DV methodologies for digital, analog, and photonic devices with emphasis on emulation
• Create and execute test plans for functional and performance goals using emulation
• Collaborate with architects, DV engineers, and designers to define validation flows
• Create reusable testbench components for efficient verification
• Close coverage and DV signoff requirements with mixed signal simulations