Tech Stack

Description

You will develop next-generation ASICs for SpaceX's Starlink network, working with cross-disciplinary teams to verify digital designs at block and system levels using SystemVerilog, UVM, and Python.

Requirements

• Bachelor's degree in electrical engineering, computer science, or computer engineering
• 1+ years of experience in design verification and test bench development
• Experience with UVM or other verification methodologies
• Strong object-oriented programming and problem-solving skills
• Experience with constrained random verification and scripting languages like Python

Responsibilities

• Digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and sequences
• Develop SystemVerilog testbench infrastructure (UVM and non-UVM), including DSP blocks
• Execute test plans, run regressions, close code and functional coverage
• Automate test case generation using Python and MATLAB