🛠 Tech Stack

💼 About This Role

You'll lead digital ASIC verification for next-generation FPGAs and ASICs deployed in space and ground infrastructure. You'll drive test plans and milestones from concept to operational capability. This role supports national security programs with a rapid prototyping mindset.

🎯 What You'll Do

• Develop block- and system-level digital ASIC verification testbenches
• Create SystemVerilog UVM and non-UVM testbench infrastructure
• Execute test plans, run regressions, and close code/functional coverage
• Automate test case generation using Python and MATLAB

📋 Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 8+ years of experience in design verification and testbench development
• Experience with UVM/OVM/VMM verification methodologies
• Proficiency in SystemVerilog testbench development

✨ Nice to Have

• Advanced degree in electrical engineering or computer engineering
• RTL design, chip bring-up, and post-silicon validation experience
• Constrained random verification and coverage modeling expertise

🎁 Benefits & Perks

• 🏖️ Paid Vacation: 3 weeks accrued annually
• 💰 Equity: Company stock, stock options, or long-term cash awards
• 🏥 Medical/Vision/Dental: Comprehensive coverage
• 📈 401(k): Retirement plan with company match
• 👶 Parental Leave: Paid family leave

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Onsite Interviews· 4 hours

🚩 Heads Up

• ITAR requirement restricts applicants to U.S. citizens/permanent residents only
• Requires ability to work long hours and weekends as necessary
• Position requires an active clearance with drug/alcohol testing