Tech Stack

Description

You will work on implementing complex SoCs for next-generation satellite and space systems, developing timing constraints and validating them from RTL handoff to synthesis. Collaborating with architecture, RTL design, DFT, and physical design teams, you'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration.

Requirements

• Experience in ASIC synthesis and timing closure
• Proficiency with synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus)
• Strong understanding of timing constraints (SDC) and STA
• Scripting skills (Python, Tcl) for automation

Responsibilities

• Work on RTL-to-Synthesis flow: synthesis at block and top level
• Work with physical design team to integrate floorplan information for physical synthesis
• Develop and maintain design methodologies, scripts, and automation to optimize PPA