Tech Stack

Description

You will implement advanced SoCs for next-generation satellite and space systems, contributing to the full physical design flow from synthesis to GDSII. You'll collaborate with cross-functional teams to achieve timing closure, optimize PPA, and support design integration, enabling the development of cutting-edge SoCs that will fly in space.

Requirements

• Proven experience in ASIC physical design, with strong background in synthesis, place & route, STA, and physical verification
• Hands-on experience with industry-standard EDA tools (Synopsys, Cadence, or Mentor)
• Proficiency in scripting languages (Tcl, Python, or Perl) for flow automation
• Experience with timing closure and optimization across multiple corners and modes
• Excellent collaboration and communication skills, ability to work with cross-functional teams and external partners

Responsibilities

• Execute complete physical design flow for complex SoC blocks and top-level integration (synthesis, floorplanning, place route, CTS, STA, physical verification)
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools
• Collaborate with front-end, verification, and DFT teams for clean handoff and predictable convergence
• Work with external physical design service providers and internal leads to review deliverables, resolve issues, ensure schedule alignment
• Support physical sign-off activities including DRC/LVS, IR drop, EM, power analysis, and assist in chip-level integration, ECOs, tapeout preparation