Tech Stack

Description

You will work alongside cross-disciplinary teams to develop cutting-edge next-generation ASICs for SpaceX's Starlink network, responsible for digital ASIC verification at block and system level, including test planning, testbench development, and coverage closure.

Requirements

• Bachelor's in EE, CS, or CompE
• 1+ years of design verification and test bench development experience
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Experience with constrained random verification

Responsibilities

• Digital ASIC verification at block and system level
• Write test plans, develop test harnesses and sequences
• Develop SystemVerilog testbench infrastructure (UVM and non-UVM)
• Execute test plans, run regressions, close code and functional coverage
• Automate test case generation using Python and MATLAB