Tech Stack

Description

You will work with a cross-functional team to verify digital, analog, and photonic designs using UVM and AMS methods. Your role involves creating test plans, developing reusable testbench components, and ensuring high-quality tapeouts through both simulation and emulation.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum 8 years of design verification and SystemVerilog experience.
• 2+ years of experience in Python.
• Expertise in developing with the UVM library.
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS.

Responsibilities

• Define and enhance DV methodologies for integrated digital, analog, and photonic devices with emphasis on emulation.
• Create and execute test plans ensuring high-quality tapeouts and functional/performance goals.
• Collaborate with architects, DV engineers, and designers to define validation flows.
• Create reusable and scalable testbench components for efficient verification.
• Close coverage and DV signoff, leveraging mixed signal simulations for high coverage metrics.