Tech Stack

Description

You will lead the development of scalable simulation and emulation environments for safety-critical FPGA systems, integrating UVM architecture, DO-254 compliance, and advanced verification techniques. This high-impact role involves building and optimizing verification ecosystems while providing technical leadership across FPGA programs.

Requirements

• Bachelor's/Master's in Electrical Engineering or related field
• 10+ years' experience in FPGA/ASIC verification
• Strong experience in DO-254 environments (DAL A/B preferred)
• Deep expertise in SystemVerilog and UVM, including scalable testbench architecture
• Direct experience with Siemens Veloce or similar emulation platforms

Responsibilities

• Architect and develop SystemVerilog/UVM-based verification environments for FPGA designs
• Build scalable, reusable testbench infrastructure (agents, monitors, scoreboards, predictors)
• Define verification strategies including sequences, constraints, and coverage models
• Leverage Siemens Veloce or similar emulation platforms to accelerate verification and debug
• Ensure verification activities align with DO-254 DAL A/B objectives and develop verification artifacts