🛠 Tech Stack

💼 About This Role

You'll lead ASIC design strategy from concept to silicon for neutral-atom quantum computers. You'll own end-to-end design decisions—performance, power, area, system integration—and establish internal design methodologies.

🎯 What You'll Do

• Lead FPGA-to-ASIC porting for higher performance and density
• Establish ASIC design processes: architecture, RTL, verification, tapeout
• Perform hands-on microarchitecture, RTL development, and integration
• Manage schedules and vendor interfaces for successful fabrication

📋 Requirements

• MS/PhD in Electrical Engineering or related field
• 10+ years post-degree ASIC/SoC experience
• 2+ complete ASIC design cycles
• RTL proficiency with SystemVerilog

✨ Nice to Have

• Mixed-signal design experience
• Knowledge of Cadence, Synopsys, or Siemens EDA tools

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter phone screen· 30 min
2. 2Technical interview· 60 min
3. 3Hiring manager interview· 45 min