Tech Stack

Description

You will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures for the Starlink network. You'll collaborate with cross-disciplinary teams to evaluate architectural trade-offs, implement RTL in Verilog/SystemVerilog, and bring designs from micro-architecture to silicon bring-up.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation
• Experience with clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with standard bus protocols (e.g. AXI, AHB) and scripting skills (e.g. Python)

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, and integrate at top level
• Work with verification team to ensure design coverage and verification
• Provide timing constraints for IPs and support physical implementation team
• Participate in silicon bring-up and validation