Tech Stack

Description

In this role, you will develop cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures, enabling connectivity in places where it was previously unavailable, affordable, or reliable. You'll evaluate architectural trade-offs, implement RTL in Verilog/SystemVerilog, and work closely with cross-disciplinary teams to expand Starlink network capabilities.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation
• Ability to solve complex problems including clock domain crossings and power optimization
• Experience with ASIC/SoC system integration
• Experience with multicore CPU subsystem design

Responsibilities

• Evaluate architectural trade-offs based on features, performance, and system limitations
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate at top level
• Deliver fully verified, synthesis/timing clean design
• Work with verification team to ensure design coverage
• Participate in silicon bring-up and validation