💼 About This Role

You'll define the safety architecture for automotive-grade AI chips, ensuring ISO 26262 compliance at the silicon level. Your work will drive fault-tolerant design across NPUs and SoCs, partnering with hardware and RTL teams. This role offers external leadership opportunities with European consortia and customers.

🎯 What You'll Do

• Own ISO 26262 safety architecture for AI-enabled SoCs (ASIL B to D)
• Integrate fault-tolerance mechanisms with RTL and SoC architects
• Lead HARA, FMEDA, FTA, and DFA analyses across hardware levels
• Act as technical lead in partner and customer safety engagements

📋 Requirements

• 5+ years of semiconductor functional safety experience (ISO 26262, ASIL B-D)
• Hands-on expertise in hardware-level safety architecture and RTL fault detection
• Proficiency in FMEDA, HARA, FTA, and DFA safety analysis methods
• Experience with SoC design workflows and embedded safety IP

✨ Nice to Have

• Experience with NPU/AI accelerator architectures
• Working knowledge of ISO/SAE 21434 and SOTIF
• Background in AI/ML-based automotive applications

🎁 Benefits & Perks

• 🏖️ Attractive compensation including pension plan and insurances
• 💰 Company shares eligibility
• 🌍 International fast-growing team with hybrid/remote options
• 📈 Creative and innovative culture with ownership