🛠 Tech Stack

💼 About This Role

You'll define micro-architecture and RTL for AI control subsystem modules at d-Matrix, a startup pushing generative AI boundaries. This role impacts high-performance hardware execution engines in a hybrid Santa Clara environment. You'll collaborate on cutting-edge processor and DSP designs for next-gen AI chips.

🎯 What You'll Do

• Define micro-architecture and design of AI control subsystem modules
• Deliver fully verified RTL meeting performance, area, and power targets
• Implement logic functions enabling efficient test and debug
• Participate in silicon bring-up and validation

📋 Requirements

• Master's in EE/CE/CS with 5+ years of meaningful work experience
• Experience in micro-architecture and RTL development (Verilog/System Verilog) focused on processor sub-systems and DSP blocks
• Exposure to Computer Architecture & Arithmetic and RISC-V/Tensilica/ARM/Mips processors
• Good understanding of ASIC design flow including RTL design, verification, synthesis, and timing analysis

✨ Nice to Have

• Experience with floating point and integer arithmetic and numerics
• Exposure to interconnect and bus interfaces

🎁 Benefits & Perks

• 💰 $196K–$300K compensation
• 🏢 Hybrid work with onsite 3-5 days/week
• 🌱 Inclusive culture with direct communication
• 🔬 Cutting-edge AI hardware projects