🛠 Tech Stack

💼 About This Role

You'll build and scale hardware-accelerated verification environments for complex, safety-critical FPGA systems using platforms like Siemens Veloce. Your work will enable full-chip validation that can't be achieved in simulation alone, making large-scale FPGA systems testable and debuggable. This role offers a $5,000 sign-on bonus and the chance to shape the future of aerospace and defense systems.

🎯 What You'll Do

• Build and maintain FPGA emulation environments using Siemens Veloce
• Port and optimize RTL and test environments from simulation to emulation
• Debug complex system-level issues that appear only in emulation
• Support validation of high-speed interfaces and system-level data flows

📋 Requirements

• 5+ years of experience in FPGA/ASIC verification or validation
• Hands-on experience with hardware emulation platforms (e.g., Siemens Veloce)
• Strong understanding of RTL design and verification workflows
• Familiarity with SystemVerilog and UVM at integration level

✨ Nice to Have

• Experience with DO-254 or other safety-critical standards
• Exposure to high-speed interfaces or communication protocols
• Experience with scripting/automation (Python, TCL)

🎁 Benefits & Perks

• 💰 $5,000 sign-on bonus
• 🏥 Comprehensive medical/dental/life insurance
• 💰 401(k) with employer match
• 📚 Professional development support and certification assistance
• 🏖️ Flexible, people-first work environment

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter phone screen· 30 min
2. 2Technical interview· 60 min
3. 3Hiring manager interview· 45 min
4. 4Offer· 1 week