🛠 Tech Stack

💼 About This Role

You'll lead STA sign-off for flagship Silicon photonics chips at advanced nodes, collaborating with architecture and RTL teams to develop timing constraints and closure flows. This role offers the chance to work on cutting-edge photonics-based interconnect solutions at a $4.4B company.

🎯 What You'll Do

• Drive STA sign-off for flagship Silicon photonics chips at various technology nodes.
• Analyze fab guidelines and incorporate sign-off corners, margins, and derates.
• Collaborate with architecture, RTL, and DFT teams to develop timing constraints and modes.
• Run full-chip STA and project timing summary across scenarios.

📋 Requirements

• 12 years of Physical Design experience with 5+ years hands-on ASIC STA
• Experience with Cadence or Synopsys timing closure tools
• Proficiency in TCL, Python, PERL, or Shell

✨ Nice to Have

• Master’s degree in Electrical Engineering or Computer Engineering
• 8+ years hands-on ASIC STA experience

🎁 Benefits & Perks

• 🏥 Comprehensive Health Care Plan (Medical, Dental, Vision)
• 💰 Retirement Savings Matching Program
• 🏖️ Generous Time Off (Vacation, Sick, Public Holidays)
• 📚 Training & Development
• 🚆 Commuter Benefits

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Call· 30 min
2. 2Technical Phone Screen· 60 min
3. 3On-site Interviews· 4 hours