Tech Stack

Description

You will design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participating in full design lifecycle from architecture through lab bring-up. Collaborate with cross-functional teams to develop cutting-edge chips enabling global connectivity.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
• 1+ years of RTL Design experience using SystemVerilog, Verilog or VHDL
• Proficiency in Python for scripting (preferred)
• Experience with EDA tools such as HDL simulators (preferred)
• Understanding of AXI/AHB/APB protocols (preferred)

Responsibilities

• Design ASICs/FPGAs using Verilog/SystemVerilog for Starlink projects
• Participate in full design lifecycle from architecture through lab validation
• Engage in high-level architectural design for FPGA and ASICs
• Collaborate with cross-functional teams on new technologies for Starlink