Tech Stack

Description

In this role, you will implement complex digital blocks at advanced process nodes (3nm) for high-performance ASICs, working alongside world-class scientists and engineers to optimize system performance and trailblaze new problems in the photonics industry.

Requirements

• Bachelor's in Electrical Engineering or Computer Engineering
• At least 8+ years of industry experience as a Physical Design Engineer
• Completed blocks or top-level physical design for large ASICs or mixed signal chips that taped out
• Thorough knowledge of timing closure, LVS/DRC closure
• Experience in TCL and Python scripting

Responsibilities

• Implement digital blocks from synthesis through physical verification using industry-standard tools
• Understand and debug timing constraints, derates, and margins; fix timing violations
• Build and customize power grid to meet power integrity goals
• Customize clock implementation for functional and test clocks
• Perform manual layouts and learn silicon photonics layout