🛠 Tech Stack

💼 About This Role

You'll join Etched to review and refine DFT flow automation for our transformer AI ASIC, working across frontend and backend teams. You'll contribute to DFT verification (MBIST, Scan, BSCAN, SSN) and develop flows for various ATPG fault models. No prior DFT experience required—just rapid learning in a high-autonomy environment.

🎯 What You'll Do

• Review and refine DFT flow automation for chip-level regression
• Contribute to DFT verification including MBIST, Scan, BSCAN, and SSN simulations
• Develop flows for various ATPG fault models (SAF, TDF, etc.)
• Work across frontend and backend design teams

📋 Requirements

• Pursuing Bachelor's, Master's, or PhD in EE, CE, or related field
• Familiarity with Verilog or SystemVerilog
• Exposure to ASIC or SoC design concepts
• Familiarity with scripting in Python, Tcl, or similar

✨ Nice to Have

• Knowledge of DFT concepts such as MBIST, scan insertion, scan compression
• Experience with Tessent or similar DFT tooling
• Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

🎁 Benefits & Perks

• 🏠 Generous housing support for relocation
• 🍽️ Daily lunch and dinner in office
• 🧑‍🏫 Direct mentorship from industry leaders
• 🚀 Work on one of the most important problems of our time

📨 Hiring Process

12-week paid internship (June-August 2026) at San Jose office with housing support.

[email protected]