🛠 Tech Stack

💼 About This Role

You'll execute full-chip and block-level physical design from RTL to GDSII, optimizing PPA for advanced AI semiconductor products in a multicultural, engineering-led team. You'll collaborate closely with RTL and packaging teams to achieve timing closure and silicon success.

🎯 What You'll Do

• Execute floorplanning, placement, clock tree synthesis, and routing
• Develop and optimize the digital backend flow
• Drive timing closure, power optimization, and physical verification
• Collaborate with front-end designers on timing and interface issues

📋 Requirements

• Master’s or PhD in Electrical/Electronic Engineering or related field
• 4+ years in digital IC backend implementation
• Proficiency with Cadence Innovus and Genus EDA tools
• Strong understanding of static timing analysis and physical verification

✨ Nice to Have

• Experience with advanced technology nodes (22nm or below)
• Skilled in Tcl scripting for backend flow automation
• Experience in hierarchical or full-chip implementation

🎁 Benefits & Perks

• 💰 Competitive cash compensation
• 📦 Meaningful stock option plan
• 🏥 Healthcare coverage including family-friendly options
• ✈️ 25 days PTO plus public holidays
• 🚗 Relocation bonus within 20 minutes of office

📨 Hiring Process

Screening call, technical meeting, CEO interview, reference calls, technical assessment, final interview.

🚩 Heads Up

• Role lists 4+ years experience but also considers PhD
• Multiple hiring steps with reference calls