🛠 Tech Stack

💼 About This Role

You'll drive STA sign-off for flagship Silicon photonics chips at leading technology nodes. Your work will directly enable AI data center interconnects at the speed of light. This role offers a chance to trailblaze new industry problems in a fast-growing company.

🎯 What You'll Do

• Drive STA sign-off for flagship Silicon photonics chips
• Analyze fab guidelines and incorporate sign-off corners into timing flows
• Collaborate with architecture, RTL, and DFT teams on timing constraints
• Run full-chip STA and project timing summary across scenarios

📋 Requirements

• Bachelor's degree in Electrical Engineering or Computer engineering
• 12 years of Physical Design experience
• 5 years hands-on experience in ASIC STA and timing closure with Cadence/Synopsys
• Proficiency in TCL and Python, PERL, or Shell

✨ Nice to Have

• Master's degree in Electrical Engineering or Computer engineering
• 8 years hands-on experience in ASIC STA and timing closure

🎁 Benefits & Perks

• 🏖️ Generous Time Off (Vacation, Sick, Public Holidays)
• 🏥 Comprehensive Health Care Plan (Medical, Dental, Vision)
• 💰 Equity grants (new hire and annual performance-based)
• 📈 Retirement Savings Matching Program
• 🚌 Commuter Benefits

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 1 hour
3. 3Hiring Manager Interview· 45 min