Description

You will lead DFT architecture and implementation for complex mixed-signal SoCs, ensuring high test coverage and manufacturability. You'll collaborate with design and verification teams to drive first-pass silicon success in a fast-paced space startup environment.

Requirements

• Deep expertise in memory BIST and TAP controller insertion at RTL
• Proficiency in scan insertion and ATPG across digital and mixed-signal domains
• Experience with DFT verification signoff including scan/ATPG coverage, DRC/Lint, and gate-level simulation
• Strong collaboration skills with RTL, DV, and PD teams
• Experience supporting silicon bring-up and debug of tester failures and yield issues

Responsibilities

• Define and implement DFT architecture for mixed-signal SoCs including scan, MBIST, LBIST, and boundary scan
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies
• Own ATPG flow development and execution for stuck-at, transition, and path delay patterns
• Drive coverage closure, pattern optimization, and debug pattern failure with silicon correlation
• Develop and integrate DFT strategies for mixed-signal blocks including analog test interfaces and BIST solutions