Tech Stack

Description

You will work with cross-disciplinary teams to develop cutting-edge ASICs for deployment in space and ground infrastructure, enabling global connectivity through the Starlink network. Responsibilities include synthesis, floorplanning, place and route, timing closure, and physical verification.

Requirements

• Bachelor's degree in EE, computer engineering, or computer science
• 1+ years professional experience with ASICs or physical design flow development
• Experience with industry standard EDA tools
• Knowledge of deep sub-micron FinFET and CMOS physics
• Scripting skills in csh/bash, Perl, Python, TCL, or Makefile

Responsibilities

• Perform synthesis, floorplanning, place and route, timing, and physical verification
• Develop physical design methodologies and automation scripts
• Collaborate with ASIC design team on architectural feasibility and timing/power/area targets
• Resolve design/timing/congestion and flow issues
• Run and debug signoff closure issues in STA, noise, logic equivalency, and electromigration