Tech Stack

Description

You will work on custom analog and RFIC layouts for Starlink silicon projects, collaborating with cross-disciplinary teams to drive integration, lower power, and advanced mixed-signal architectures for space and ground infrastructure.

Requirements

• Bachelor's in EE or CE with 1+ year IC layout exp, or 3+ years IC layout exp without degree
• Strong analog layout skills
• Experience with advanced node IC layouts (22nm, 16nm, 7nm, etc.)
• Experience with layout of circuits up to 50GHz and sensitive RF blocks (LNA, VCO, mixers)
• Skill programming; shell scripting, Perl, or Python; Linux proficiency

Responsibilities

• Work with IC designers to determine chip floor plan, including power/ground distribution and pad locations
• Perform custom RF and analog block layout with emphasis on matching and parasitic minimization
• Execute DRC, ERC, and LVS checks and resolve errors
• Perform top-level layout integration with ESD structures and final tapeout
• Work with EDA suppliers to trial new tools and generate improvement guides