Tech Stack

Description

As a Design Verification Engineer at SpaceX, you will develop cutting-edge ASICs for the Starlink network, verifying digital designs at block and system level. You will work with cross-disciplinary teams to ensure chip quality and help expand connectivity globally.

Requirements

• Bachelor's degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Scripting experience (e.g., Python) for automation

Responsibilities

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (UVM and non-UVM)
• Execute test plans, run regressions, achieve code and functional coverage closure
• Automate test case generation using Python and MATLAB