🛠 Tech Stack

💼 About This Role

You'll partner with design and architecture teams to translate hardware specifications into comprehensive verification plans. You'll drive the development of testbenches and coverage metrics to validate mission-critical functionality. This role offers a hybrid schedule working on one of the world's highest performance automotive compute platforms.

🎯 What You'll Do

• Translate hardware specifications into comprehensive verification plans
• Develop testbenches, reference models, and stimulus for functional validation
• Architect and enhance verification environments with reusable methodologies
• Define and analyze coverage metrics (functional and code) for design readiness

📋 Requirements

• 3+ years of experience with UVM/SystemVerilog testbenches
• Proven track record with constrained-random generation and functional coverage
• Deep understanding of complex digital logic and hardware/software debug
• Proficiency in Python for automation frameworks and data analysis

✨ Nice to Have

• Experience spanning specification through post-silicon bring-up
• Familiarity with power-aware verification (UPF) or formal verification
• Domain expertise in ML accelerators or high-speed interconnects

🎁 Benefits & Perks

• 💰 Discretionary annual bonus program
• 📈 Equity incentive plan
• 🏥 Generous Company benefits program