Tech Stack

Description

As a Sr. RTL Design Engineer at SpaceX, you will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructure, enabling global connectivity through the Starlink network. You'll collaborate with cross-disciplinary teams to evaluate architectural trade-offs, implement RTL, and support silicon bring-up and validation.

Requirements

• Bachelor's in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation
• Experience with clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems and standard bus protocols (AXI, AHB)

Responsibilities

• Evaluate architectural trade-offs based on features, performance, and system limitations
• Define micro-architecture and implement RTL in Verilog/SystemVerilog
• Integrate blocks at top level and deliver verified, synthesis/timing clean design
• Work with verification team to ensure design coverage and verification
• Provide timing constraints and support physical implementation team