Tech Stack

Description

You will verify the functionality, performance, and robustness of custom silicon designs in a fast-paced space startup. You'll define verification approaches, build test benches, and collaborate closely with cross-functional teams to shape first-generation silicon.

Requirements

• Proven experience in ASIC design verification
• Deep knowledge of SystemVerilog and UVM
• Experience with assertion-based verification and formal methods
• Ability to work collaboratively in a fast-paced startup environment

Responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments
• Build SystemVerilog/UVM test benches including agents, monitors, scoreboards, checkers, and coverage models
• Write SystemVerilog Assertions (SVA) and integrate formal verification