🛠 Tech Stack

💼 About This Role

You'll own full-chip physical verification signoff for cutting-edge silicon powering the Starlink network. You'll work with cross-disciplinary teams to deliver chips enabling global connectivity. This role offers the chance to solve complex challenges at advanced technology nodes.

🎯 What You'll Do

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff
• Develop and optimize physical verification flows for advanced node SoCs
• Interpret foundry Design Rule Manuals and implement verified flow changes
• Drive tapeout readiness by coordinating signoff across teams

📋 Requirements

• Bachelor's degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience
• Experience with industry standard tools like Calibre, ICV, or Pegasus
• Hands-on proficiency in DRC, LVS, PERC and ESD verification

✨ Nice to Have

• SOC top level physical design flows experience
• IP integration experience (memories, I/O, analog IPs, SerDes, DDR)
• Experience at advanced nodes (4nm and below)

🎁 Benefits & Perks

• 🏥 Comprehensive medical, vision, and dental coverage
• 🏦 401(k) retirement plan
• 📈 Long-term incentives (stock, options, cash awards)
• 👶 Paid parental leave
• 🏖️ 3 weeks paid vacation plus 10+ holidays

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Onsite Interview· 4 hours

🚩 Heads Up

• Requires ability to work extended hours and weekends as needed