Tech Stack

Description

You will lead DFT architecture implementation and optimization for next-generation ASICs used in the Starlink network, working with cross-disciplinary teams to enable connectivity worldwide. This role involves owning ATPG methodologies, supporting post-silicon validation, and developing test automation scripts.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience working with ASICs
• 10+ years of experience in scan insertion and DFT setup, integration, and validation
• Experience with UPF, formal verification, and DRC rule checking
• Ability to work extended hours and weekends as needed

Responsibilities

• Lead implementation and optimization of DFT architectures including scan insertion, compression/decompression, memory BIST, and logic BIST using Siemens Tessent tools
• Own ATPG methodologies and generate patterns for stuck-at, transition, and path delay fault models
• Provide post-silicon testing and validation support
• Evaluate design readiness for scan insertion through RTL and physical design
• Develop test scripts and automate processes using Perl, Python, Tcl, or C+