Tech Stack

Description

You will develop cutting-edge FPGAs and ASICs for space and ground infrastructures, working on advanced defense programs. Collaborate cross-functionally to partition functions, implement RTL, and support silicon bring-up.

Requirements

• Bachelor’s in EE, CompE, or CS
• 8+ years RTL implementation or FPGA/ASIC development
• Experience with clock domain crossings and power optimization
• Experience with bus protocols (AXI, AHB)
• Scripting skills (Python, TCL)

Responsibilities

• Design digital ASICs and/or FPGAs for Starshield projects
• Evaluate architectural trade-offs based on features, performance, and system limitations
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate at top level
• Provide timing constraints and support physical implementation
• Participate in silicon bring-up and validation