Tech Stack

Description

You will develop cutting-edge FPGAs and ASICs for space and ground infrastructures, defining micro-architecture, implementing RTL, and collaborating with cross-disciplinary teams to expand Starlink network performance and capabilities.

Requirements

• Bachelor's degree in EE, CE, or CS
• 5+ years of experience in RTL implementation
• Experience with bus protocols (AXI, AHB)
• Scripting skills (Python, TCL)
• Experience with EDA tools (VCS, Vivado, etc.)

Responsibilities

• Evaluate architectural trade-offs based on features, performance, and system limitations
• Define micro-architecture and implement RTL in Verilog/SystemVerilog, integrating at top level
• Work with verification team to ensure full design coverage and verification
• Provide timing constraints and support physical implementation team
• Participate in silicon bring-up and validation