🛠 Tech Stack

💼 About This Role

You'll design and implement key compute, memory, and interconnect components for OpenAI's custom AI accelerator. Your work will directly impact the performance of next-generation AI models by creating efficient hardware structures. You'll collaborate closely with architecture, verification, and ML engineers to translate AI workloads into production-quality RTL.

🎯 What You'll Do

• Produce microarchitecture and RTL for major accelerator subsystems
• Contribute to architectural studies and performance modeling
• Collaborate with software and compiler teams for hardware/software co-design
• Partner with DV and PD teams for timing closure and integration

📋 Requirements

• SystemVerilog/Verilog RTL design experience with tape-out track record
• Experience in computer architecture and AI/ML hardware-software co-design
• Familiarity with industry-standard design tools and methodologies
• Ability to work cross-functionally with architecture, ML, and verification teams

✨ Nice to Have

• Experience developing hardware design models or architectural simulators
• Knowledge of AI/ML workload analysis and dataflow mapping
• Passion for building massive-scale hardware systems

🎁 Benefits & Perks

• 💰 Competitive equity package
• 🏠 Hybrid work model (3 days in office per week)
• 🚚 Relocation assistance available
• 🏥 Comprehensive health benefits

🚩 Heads Up

• This role includes background checks and export control compliance
• Role may require legal status requirements per U.S. export laws