🛠 Tech Stack

💼 About This Role

You'll design and validate test solutions for multicore in-memory-compute SoCs at a fast-growing AI startup. You'll improve silicon testability and contribute to cutting-edge architectures. Collaborate with a talented European team in a flexible remote or hybrid setting.

🎯 What You'll Do

• Implement scan insertion, ATPG, Memory BIST, and JTAG/IJTAG flows.
• Collaborate with RTL, verification, and physical design teams.
• Support silicon bring-up, debug, and optimize test coverage.
• Contribute to DFT methodology improvements and best practices.

📋 Requirements

• 5+ years of DFT engineering experience with complex SoCs.
• SystemVerilog RTL and TCL or Python skills.
• Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG knowledge.
• Siemens, Synopsys, or Cadence DFT tool experience.

✨ Nice to Have

• Familiarity with IEEE 1149.x, 1500, or 1687 standards.
• Synthesis flow and timing analysis experience.

🎁 Benefits & Perks

• 💰 Attractive compensation with pension and insurance.
• 📈 Company shares option.
• 🌍 Flexible remote across Europe or on-site options.