💼 About This Role

You'll drive full-chip tape-out programs across RTL, DFT, DV, and Physical Design teams. Your core impact is owning external vendor relationships and ensuring first-silicon success. This role offers direct influence on the world's first transformer-specific AI inference chip.

🎯 What You'll Do

• Coordinate across Physical Design, DFT, DV, and RTL teams
• Manage external vendors including EDA and implementation partners
• Identify critical path risks and develop mitigation strategies
• Communicate program status to engineering leads and executives

📋 Requirements

• At least one full ASIC tape-out experience
• 5+ years in technical program management in semiconductor/hardware
• Solid understanding of RTL-to-GDSII flow
• Experience working with external EDA vendors

✨ Nice to Have

• Familiarity with synthesis, DFT insertion, and ECO cycles
• Experience in fast-paced startup environments
• Strong facilitation and mediation skills

🎁 Benefits & Perks

• 🏥 Medical, dental, vision with generous premium coverage
• 💵 $500/month for waiving medical benefits
• 🏠 $2k/month housing subsidy for walking distance to office
• 🚚 Relocation support to San Jose (Santana Row)
• 🍽️ Daily lunch and dinner provided

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Onsite Round· 4 hours