Tech Stack

Description

You will own the creation of behavioral models and drive mixed-signal verification methodology for state-of-the-art SoCs used in large, high-power satellites. Your work will directly influence top-level integration and silicon tapeout success.

Requirements

• Own mixed-signal verification methodology from the ground up
• Collaborate with analog/RF designers to capture real-world analog behaviors into accurate behavioral abstractions
• Work with digital and verification teams for seamless integration of AMS models
• Support architectural exploration through early-phase modeling and system-level simulations

Responsibilities

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers)
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog)
• Integrate AMS models into digital verification environments (UVM-based)
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification