🛠 Tech Stack

💼 About This Role

You'll design digital ASICs and FPGAs for Starshield, a program leveraging SpaceX's Starlink technology for national security. You will evaluate architectural trade-offs and drive designs from micro-architecture to silicon bring-up. This role offers the chance to work on cutting-edge space and ground infrastructure for U.S. National Security.

🎯 What You'll Do

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate architectural trade-offs based on features and performance.
• Define micro-architecture and implement RTL in Verilog/SystemVerilog.
• Work with verification team to ensure full design coverage.
• Provide timing constraints and support physical implementation.

📋 Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 8+ years of experience in RTL implementation and/or FPGA/ASIC development.
• Experience with clock domain crossings and power optimization.
• Ability to work long hours and weekends as necessary.

✨ Nice to Have

• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Scripting skills in Python or TCL.

🎁 Benefits & Perks

• 💰 Base salary $200,000 - $285,000/year
• 📈 Long-term incentives including stock options and cash awards
• 🏥 Comprehensive medical, vision, and dental coverage
• 🏖️ 3 weeks paid vacation plus 10+ holidays
• 👶 Paid parental leave

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Hiring Manager Interview· 45 min

🚩 Heads Up

• Requires long hours and weekends as necessary
• Active TS-SCI clearance may be required with drug testing
• ITAR restrictions require U.S. citizenship or specific resident status