Tech Stack

Description

You will architect and implement digital subsystems for advanced wireless SoCs used in high-power satellites, working on cutting-edge mixed-signal designs from concept through spaceflight.

Requirements

• B.S./M.S. in EE, CE, or related field with 2+ years digital ASIC design experience
• Proficiency in RTL design (SystemVerilog/Verilog), synthesis, and linting tools
• Experience in micro-architecture definition and DFT tools for scan and BIST
• Solid understanding of SoC design flows (clock/power domain crossing, timing constraints)
• Experience implementing DSP functions in hardware

Responsibilities

• Design and verify digital blocks for wireless SoCs using SystemVerilog/Verilog
• Translate algorithmic specs into synthesizable RTL, implement DSP functions
• Design RTL for interfaces, power management, clocking, reset, test debug
• Partner with analog teams, optimize power/performance/area, support timing closure
• Participate in chip bring-up and lab validation, support through production and spaceflight