1d ago

Power Validation Engineer

San Jose

โœจ $130k-$200k / yearest.

full-timemidai-ml

๐Ÿ›  Tech Stack

๐Ÿ’ผ About This Role

You'll own the end-to-end power characterization of our ASIC and mezzanine card platform, from early silicon bring-up through production qualification. You'll design measurement methodology, build test benches, and drive findings directly into silicon and system design decisions. This role offers the opportunity to work on cutting-edge AI inference hardware backed by top-tier investors.

๐ŸŽฏ What You'll Do

  • Design and execute power measurement campaigns across all voltage rails under LLM inference workloads.
  • Validate PDN performance and translate measurements into feedback for PCB and package design.
  • Profile power transient events and correlate with on-die performance monitor data.
  • Run extended stress workloads to surface reliability risks and throttling behavior.
  • Validate power sequencing, PMBus telemetry, and BMC alert thresholds.

๐Ÿ“‹ Requirements

  • Bachelor's degree in Electrical Engineering or related field.
  • Deep understanding of ASIC and system-level power delivery with hands-on bench experience.
  • Expertise with multi-phase VR solutions and VR tuning to meet CPU/ASIC specifications.
  • Demonstrated ability to design experiments for root cause isolation in complex hardware-software stack.
  • Relevant experience with Silicon bring-ups.

โœจ Nice to Have

  • Masters Degree in Power Electronics.
  • Experience with high voltage testing (800V and higher).
  • Prior power validation work on AI accelerators, GPUs, or high-performance server platforms.
  • Experience with OpenBMC, IPMI, or custom BMC firmware.

๐ŸŽ Benefits & Perks

  • ๐Ÿฅ Medical, dental, and vision with generous premium coverage.
  • ๐Ÿ’ฐ $500/month credit for waiving medical benefits.
  • ๐Ÿ  Housing subsidy of $2k/month for living within walking distance of office.
  • ๐Ÿšš Relocation support for moving to San Jose (Santana Row).
  • ๐Ÿฝ๏ธ Daily lunch and dinner in the office.

๐Ÿ“จ Hiring Process

Estimated timeline: 2-4 weeks ยท AI estimate

  1. 1Recruiter Screenยท 30 min
  2. 2Technical Phone Interviewยท 60 min
  3. 3Onsite Interviewsยท 4 hours
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