🛠 Tech Stack

💼 About This Role

You'll develop cutting-edge next-generation ASICs for SpaceX's Starlink network. You'll collaborate with cross-disciplinary teams to drive feasibility studies and resolve design issues, enabling global connectivity.

🎯 What You'll Do

• Perform synthesis, floorplanning, place and route, and signoff tasks
• Develop physical design methodologies and automation scripts
• Collaborate with ASIC design team on architecture and tradeoffs
• Resolve timing, congestion, and signoff closure issues

📋 Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 3+ years of professional experience in RTL2GDSII physical design or physical design flow development

✨ Nice to Have

• Experience with industry standard EDA tools
• Knowledge of deep sub-micron FinFET and CMOS physics
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile)

🎁 Benefits & Perks

• 🏖️ Paid Vacation: 3 weeks accrued annually
• 🏥 Medical, Vision, Dental: Comprehensive coverage
• 💰 401(k) Retirement Plan: Access to retirement savings
• 📈 Stock Options: Eligibility for long-term incentives including stock
• 👶 Paid Parental Leave: Leave for new parents

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Call· 30 min
2. 2Technical Interview· 60 min
3. 3Onsite Interview· 4 hours

🚩 Heads Up

• Requires ability to work extended hours and weekends as needed