🛠 Tech Stack

💼 About This Role

You'll drive verification strategy and test plan creation for complex mixed-signal SoCs. You'll collaborate with RTL and analog teams to develop verification flows. Use industry-standard tools like UVM and System Verilog to deliver high-quality designs.

🎯 What You'll Do

• Develop verification test plans and test benches.
• Write and debug SystemVerilog/UVM test cases.
• Analyze code coverage, functional coverage, and assertions.
• Run gate-level simulations and improve verification flows.

📋 Requirements

• 5+ years of experience in digital verification.
• Expertise in SystemVerilog and UVM.
• Experience with test plan creation and coverage analysis.
• Strong skills in debugging and problem solving.

✨ Nice to Have

• Knowledge of Python or TCL scripting.
• Experience with DSP or datapath verification.
• Familiarity with formal verification flows.