Tech Stack

Description

You will design digital ASICs and FPGAs for Starlink, evaluating architectural trade-offs and implementing RTL in Verilog/System Verilog. You'll work closely with cross-disciplinary teams to deliver cutting-edge chips for space and ground infrastructure, expanding the Starlink network's performance and capabilities.

Requirements

• Bachelor's in EE, CE, or CS
• 10+ years experience in RTL/FPGA/ASIC development
• Experience with clock domain crossings and power optimization
• Experience with multicore CPU subsystem design
• Scripting skills (Python, TCL)

Responsibilities

• Design digital ASICs/FPGAs for Starlink
• Evaluate architectural trade-offs based on features and performance
• Define micro-architecture, implement RTL in Verilog/SystemVerilog
• Provide timing constraints and support physical implementation
• Participate in silicon bring-up and validation