Tech Stack

Description

You will design next-generation FPGAs and ASICs for Starlink satellites and ground infrastructure, working with cross-disciplinary teams to evaluate architectural trade-offs, implement RTL in Verilog/SystemVerilog, and support silicon bring-up. Your work will expand the performance and capabilities of the Starlink network, delivering connectivity to underserved areas globally.

Requirements

• Bachelor's degree in EE, CE, or CS
• 10+ years of experience in RTL implementation and/or FPGA/ASIC development
• Experience solving clock domain crossings and power optimization
• Experience with standard bus protocols (AXI, AHB) and EDA tools
• Scripting skills (Python, TCL)

Responsibilities

• Design digital ASICs and/or FPGAs for Starlink projects
• Evaluate architectural trade-offs based on features and performance requirements
• Define micro-architecture and implement RTL in Verilog/SystemVerilog
• Provide timing constraints and support physical implementation team
• Participate in silicon bring-up and validation