🛠 Tech Stack

💼 About This Role

You'll take end-to-end ownership of physical implementation for OLIX's next-generation accelerator silicon, from floor-planning to tape-out. You will architect full-custom analog and mixed-signal layouts in advanced CMOS FinFET nodes and partner with circuit, optical, and digital teams delivering high-performance blocks for breakthrough AI hardware. You'll also lead internal and external design-services partners on multi-project tape-outs.

🎯 What You'll Do

• Execute full-custom analog and mixed-signal layouts in advanced FinFET nodes.
• Own floor-planning, power-grid design, and signal-integrity strategy.
• Lead block- and chip-level AMS integration and physical verification.
• Develop layout automation with SKILL scripts and parameterized PCells.
• Manage tape-out, ECOs, and cross-functional coordination with package and test teams.

📋 Requirements

• 8+ years of full-custom analog and mixed-signal IC layout experience.
• At least 3 taped-out products with high-speed analog content.
• Tape-out experience in advanced CMOS FinFET (16nm or below).
• Expert command of Cadence Virtuoso platform and physical verification tools.

✨ Nice to Have

• Tape-out experience at 7nm or below with multi-patterning.
• Advanced PCell development for on-chip passives.
• Familiarity with coherent optical links or photonic-electronic co-design.

🎁 Benefits & Perks

• 💰 Competitive Salary: £206,000 base salary.
• 📈 Equity: Meaningful stock options.
• 🚗 Proximity Bonus: £24k annual if within 20 minutes of office.
• 🏥 Premium Healthcare: BUPA medical and dental cover.
• 🏖️ Time Off: 25 days annual leave plus UK bank holidays.

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter phone screen· 30 min
2. 2Technical interview with hiring manager· 60 min
3. 3Onsite or virtual technical panel· 120 min