Tech Stack

Description

You will lead a team of digital ASIC engineers to design and implement advanced mixed-signal SoCs for space applications. You'll take ownership of digital blocks, manage schedules, and contribute to cutting-edge communication systems for the largest satellites ever built.

Requirements

• B.S. or M.S. in Electrical Engineering or Computer Engineering
• 10+ years industry experience in digital ASIC design
• 3+ years leading ASIC design teams or projects
• Strong proficiency in SystemVerilog or Verilog RTL design
• Experience with timing closure and synthesis tools

Responsibilities

• Lead and manage a team of digital design engineers
• Design microarchitecture and RTL for digital blocks in wireless SoCs
• Collaborate with system architects to translate DSP algorithms into hardware
• Optimize designs for power, performance, and area
• Contribute to chip bring-up and lab validation