Tech Stack

Description

You will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures, enabling connectivity worldwide. Working alongside cross-disciplinary teams, you'll contribute to the Starlink network by evaluating architectural trade-offs, implementing RTL in Verilog/SystemVerilog, and participating in silicon bring-up and validation.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation
• Experience with ASIC/SoC system integration
• Experience with embedded CPU subsystems and standard bus protocols (AXI, AHB)
• Scripting skills (e.g., Python)

Responsibilities

• Evaluate architectural trade-offs based on features, performance, and system limitations
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, and integrate at top level
• Work with verification team to ensure all aspects are covered and verified
• Provide timing constraints and support physical implementation team
• Participate in silicon bring-up and validation