🛠 Tech Stack

💼 About This Role

You'll lead the layout of high performance CMOS data converters in advanced process nodes (2nm to 28nm). Your work will directly impact cutting-edge analog and mixed-signal chips for high-speed applications. This role offers the chance to own complex blocks like ADC, DAC, PLL, and SERDES in a hybrid environment.

🎯 What You'll Do

• Lead layout of high-speed analog blocks (ADC, DAC, PLL, SERDES)
• Drive physical verification (DRC, LVS, DFM, ERC, EM, IR)
• Implement advanced layout techniques (common centroid, interdigitation, shielding, EM-aware routing)
• Define and adhere to project schedule and methodology

📋 Requirements

• 10+ years in high performance analog layout in advanced CMOS nodes
• Experience with high-speed analog blocks (ADC, DAC, PLL, SERDES)
• Proficiency in analog layout techniques (common centroid, interdigitation, shielding, dummy devices, EM-aware routing)
• Familiarity with physical verification checks (DRC, LVS, DFM, ERC, EM, IR)

✨ Nice to Have

• Experience with layout automation using SKILL/PERL/Python
• Ability to lead projects and define schedules