🛠 Tech Stack

💼 About This Role

You'll define and implement comprehensive DFT strategies for complex SoC designs targeting 5G, IoT, and LEO satellite communications. You'll ensure robust testability and quality of silicon from early design stages through manufacturing tests.

🎯 What You'll Do

• Define and implement DFT architecture for complex SoC designs
• Insert and verify scan chains using industry-standard DFT tools
• Own full ATPG lifecycle including ATE bring-up
• Develop DFT automation scripts and integrate DFT flows

📋 Requirements

• MS/PhD in Electrical Engineering or related field
• 8+ years of hands-on DFT experience for complex ASICs/SoCs
• Experience with Synopsys DFT Compiler or Tessent
• Expertise in scan insertion, ATPG, and fault simulation

✨ Nice to Have

• Experience with IEEE P1838 or die-to-die interface test
• Familiarity with ATE platforms (Advantest, Teradyne)
• Background in satellite communication or 5G NR

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Hiring Manager· 45 min