Tech Stack

Description

You will lead digital ASIC/FPGA verification at block and system level, developing test plans and executing verification for next-generation chips used in SpaceX's Starlink network. Collaborate with cross-disciplinary teams to deliver cutting-edge solutions for global connectivity.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience with design verification and test bench development
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Expertise in constrained random verification

Responsibilities

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation