🛠 Tech Stack

💼 About This Role

You'll lead verification of custom ASICs for satellite and wireless telephony at E-Space, a company building a hyper-scaled IoT space system. Your work will directly impact chip tapeout success and space-based communications innovation.

🎯 What You'll Do

• Build UVM verification environments from scratch
• Write and maintain test plans and test suites
• Debug complex RTL and gate-level simulations
• Lead code coverage closure efforts

📋 Requirements

• Verilog and SystemVerilog expert-level proficiency
• Proven experience building UVM environments from scratch
• 10+ years of design verification experience
• Proficient in C/C++ for verification

✨ Nice to Have

• VHDL experience
• Perl or Python scripting skills
• Gate-level simulation with SDF back-annotation

🎁 Benefits & Perks

• 🚀 Work on cutting-edge space technology
• 🏥 Health insurance
• 💰 Competitive equity package
• 🏖️ Flexible PTO
• 📚 Learning and development budget

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Hiring Manager Interview· 45 min

🚩 Heads Up

• Requires 10+ years of experience but title suggests principal level (may be underleveled)
• Mentions AI assistance but unclear how it's integrated