🛠 Tech Stack

💼 About This Role

You'll ensure custom IPs powering Sohu—including systolic arrays, DMA engines, and NoCs—are robust and silicon-ready. You'll collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. This role demands deep technical ability and tackling verification challenges.

🎯 What You'll Do

• Develop UVM/SystemVerilog testbenches for high-performance IPs.
• Define and execute verification plans covering correctness and performance.
• Debug datapath and protocol issues in RTL and testbench.
• Partner with SW, FW, and emulation teams for end-to-end coverage.

📋 Requirements

• Proficiency with UVM and SystemVerilog.
• Strong debugging and problem-solving skills for complex digital designs.
• Solid knowledge of computer architecture and digital design fundamentals.
• Hands-on experience verifying datapaths, memory systems, or interconnects.

✨ Nice to Have

• Familiarity with SystemVerilog Assertions (SVA) and formal verification.
• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
• Scripting skills (Python/Perl/TCL) for automation and regression flows.

🎁 Benefits & Perks

• 🏥 Medical, dental, and vision with generous coverage.
• 💰 $500/month credit for waiving medical benefits.
• 🏠 Housing subsidy of $2k/month within walking distance of office.
• 🚚 Relocation support for moving to San Jose.
• 🍽️ Daily lunch + dinner in office.